Interconnect parasitic resistance (R) and capacitance (C) elements will become the most significant problems as the semiconductor technologies (complementary-metal-oxide semiconductor or CMOS, bipolar, bipolar complementary metal-oxide-semiconductor or BiCMOS scale below 0.5 (.mu.m) micrometers. The parasitic resistance and capacitance elements associated with the aluminum-based (or refractory metal-based) metallization systems can degrade the circuit electrical performance due to the RC-induced propagation delays. Moreover, these interconnect parasitic elements increase the overall chip power dissipation and increase the amount of signal cross talk. As a result, conception and development of suitable low-RC-multi-level interconnect technologies will be among the most important and critical enablers for scaling advanced semiconductor technologies well below 0.5 .mu.m a minimum features for ultra-large-scale integrated (ULSI) system applications.